1. Field of the Invention
The invention relates generally to semiconductor packaging structures and, in particular, to interconnections between organic semiconductor modules and substrates such as printed wiring boards.
2. Description of the Related Art
Retention hardware incorporated into semiconductor packages often exerts excessive stress upon semiconductor modules and especially onto semiconductor modules designed with low insertion force or designed to be field replaceable. Excessive stress can cause reliability concerns for a semiconductor package. For example, the stress induced by retention hardware in land grid array or similar connection schemes used to connect organic modules to printed wiring boards can result in cracking, bowing, poor interconnect integrity, etc. The present invention, therefore, presents a low insertion force/low stress interconnect scheme.